The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which a structure of a trenched capacitor as a memory portion is improved.
In semiconductor memory devices such as a dynamic memory, a memory capacity thereof has been rapidly increasing in accordance with advances in micropatterning techniques. Along with increases in the capacity of the memory, memory cell area has also been increasing. However, a capacitance of a memory cell must be maintained at a sufficiently large value, i.e., several tens of fF in order to keep the S/N ratio at a proper level for preventing a soft error and for sensing by a sense amplifier.
In order to increase a capacitance per unit area, a thin insulation film of a MOS structure of a memory capacitor can be formed, or a silicon nitride film can be used as an insulation film material. However, since memory capacitors having a MOS structure are formed on a surface of a semiconductor substrate, a capacitance thereof is limited in accordance with micropatterning of the cell area.
Thus, H. Sunami et al. developed and proposed a MOS memory cell having a corrugated capacitor of a structure shown in FIG. 1 which is described in detail in "A Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories," International Electric Device Meeting Technical Digest, lecture No. 26.9, pp. 806 to 808, December, 1982. In FIG. 1, reference numeral 1 denotes a p-type silicon substrate. A deep groove 2 (e.g., 3 to 5 .mu.m) is formed so as to extend from a surface of the substrate 1 to a certain depth thereof. A capacitor electrode 3 formed of a first polycrystalline silicon layer is insulated by a capacitor insulation film 4 and extends from a bottom portion of the groove 2 to a level above an opening thereof. The capacitor insulation film 4 has a three-layered structure of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2. A trenched capacitor 5 consists of the substrate 1, the groove 2, the capacitor insulation film 4 and the capacitor electrode 3. N.sup.+ -type source and drain regions 6 and 7 which are electrically isolated from each other are provided in a region of the silicon substrate 1 adjacent to the trenched capacitor 5. A gate electrode 9 formed of a second polycrystalline silicon layer is formed on a gate oxide film 8 in a region of the substrate 1 which includes a portion between the n.sup.+ -type source and drain regions 6 and 7. A transfer transistor 10 consists of the source and drain regions 6 and 7, the gate oxide film 8 and the gate electrode 9. Furthermore, the source region 6 contacts with the insulation film 4 of the trenched capacitor 5, and the drain region 7 is connected to a bit line (not shown). In FIG. 1, reference numeral 9' denotes a gate electrode of an adjacent memory cell.
However, in the MOS memory cell shown in FIG. 1 described above, when the trenched capacitor of one of two adjacent memory cells is formed closely to the other trenched capacitor, a punch through phenomenon easily occurs, thereby causing interference of data. More specifically, a junction capacitance between a drain and a substrate of a transfer transistor of a momory cell must be decreased so as to decrease a bit line capacitance. For this reason, a concentration of a p-type silicon substrate is decreased, but, a depletion layer is thereby easily formed in a substrate region near a capacitor with the MOS structure, thereby easily causing the punch-through phenomenon. For this reason, a distance between the trenched capacitors of the two adjacent memory cells cannot be shortened, and high density memory cannot therefore be realized. The punch-through phenomenon can be avoided by doping a silicon substrate with impurity ions. However, in the trenched capacitor 5 which has the deep groove 2 in the silicon substrate 1 as shown in FIG. 1, it is difficult to ion-implant an impurity in a deep portion of the substrate 1. Thus, it is difficult to prevent the punch-through phenomenon from occurring between regions near the bottom portions of the two adjacent trenched capacitors. Therefore, in a conventional structure, the trenched capacitors of two adjacent memory cells must be spaced by a large distance from each other, thus preventing a high-density memory cell from being realized.
In the structure of FIG. 1, since a depletion layer extends from the trenched capacitor 5 in a deep portion of the silicon substrate 1, an electric charge generated by irradiation of an .alpha.-ray easily concentrates by a funneling phenomenon. For this reason, in this structure, a soft error easily occurs.